Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference
Logic synthesis has been applied to the VHDL netlists generated by the formal synthesis phase. ... A a#39;manuallya#39; optimized implementation (imp_ref) is is taken ... Workshop on Specification and Synthesis of Digital Systems, Milano (1992) [7] C. Bolchini, M. Bombana, P. Cavalloro, ... [9) R. Schlor, W. Damm, aquot;Specification and verification of system - level hardware designs using timing diagramsaquot;, Proc.
| Title | : | Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference |
| Author | : | IFIP WG 10.5, IEEE Computer Society, International Federation for Information Processing |
| Publisher | : | - 1995 |
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