Cost-effective Interconnect and Circuit Design Methods for High-speed Nanometer CMOS VLSI Design

Cost-effective Interconnect and Circuit Design Methods for High-speed Nanometer CMOS VLSI Design

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The semiconductor industry has been following Moore's law over the past five decades because of the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density, lower energy per transition, and better design performance. On the other hand, many new design problems have been introduced due to scaling, and these problems become more significant when migrating from one technology node to a newer one with smaller feature size.One of the major causes of interconnect delay degradation is the high cross- coupling capacitance between adjacent signal wires in deep submicron technologies. This is mainly due to the dense wiring employed to achieve high integrationanbsp;...


Title:Cost-effective Interconnect and Circuit Design Methods for High-speed Nanometer CMOS VLSI Design
Author: Charbel J. Akl
Publisher:ProQuest - 2008
ISBN-13:

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